In a multiple processor data processing system, the transfer bus has the purpose of transmitting data between a transmitting unit and a receiving unit of the system. The system comprises a bus control logic circuit which takes charge of all the calls coming from the transmitting and receiving units and relating to the utilization of the transfer bus. The utilization of this bus occurs in accordance with a fixed or constant priority. Each unit is given a fixed priority and in case of simultaneous calls, the priority circuit takes charge of the call originating from the unit having the highest priority. The bus control logic circuit may be placed in communication with all the units of the system to provide particular data and particular signals in respect of the state and chronology of the system.
This known system has at least two disadvantages. Since there is only one bus control circuit, breakdown of the bus control logic circuit causes all the other units of the system to stop operating. In addition, establishment of connections between transmitting and receiving units is performed by an exchange of address and acknowledgment signals, which takes time.
One solution to these problems involves installing control logic circuitry of the transmission bus into each important unit of the system at the rate of no more than one circuit per unit. Each control logic circuit takes charge of all the calls coming from the units connected to the transmission bus as well as of the calls coming from the particular unit in which it is situated and relating to the utilization of the transmission bus. Each unit is given a fixed priority enabling the same to utilize the transmission bus in accordance with an order of priority. All the control logic circuits are equipped with the same priority circuit for locating the call coming from the unit having the highest priority. All the units are thus apprised of all the units which are calling and by means of its control logic circuit, each unit may recognize itself as having the highest priority for securing control over the transmission bus. Accordingly, failure of a control logic circuit of one unit no longer impedes the operation of the other units. It is only the unserviceable unit which interrupts its interchanges with the others. It is thus no longer necessary to await the acknowledgment of the unit called, since the transfer authorization is produced locally and simultaneously made known to all the other units. In order to secure satisfactory performance in respect of the number of data exchanges on the transmission bus, however, it is necessary to render it possible to multiplex the data exchanged between units, simultaneously in space and time.